Yes, you do need to spend more energy sending data between chiplets. Intel has been relentlessly optimizing that and is probably the furthest ahead of the game on that, with EIMB and Foveros. AMD just got to a baseline sea-of-wires, where they arent using power hungry PHY to send data, and that is only shipping on Strix Halo at the moment & is slated to be a big change for Zen6. But Intel's been doing all that and more, IMO. https://chipsandcheese.com/p/amds-strix-halo-under-the-hood https://www.techpowerup.com/341445/amd-d2d-interconnect-in-z...

That also has some bandwidth constraints on your system too.

There's the labor cost of doing package assembly! Very non trivial, very scary, very intimidating work. Just knowing that TSMC's Arizona chips have to be shipped back to Taiwan, assembled/packaged there, then potentially shipped where-ever is anec-data but a very real one. This just makes me respect Intel all the more, for having such interesting chips, such as Lakefield ~6 years ago, and their ongoing pursuit of this as a challenge.

So yeah, there are many optimal aspects to a single die. You're making a problem really hard by trying to split it up across chips.

It's not even clear why we want multi chip. As a consumer, if you had your choice, yes, you are right: we do want a big huge slab of a chip. There aren't many structural advantages for us, to get anything other than what we want, on one big chip.

And yet. Your cost savings can potentially be fantastically huge. Yields increase as your square millimeter-age shrinks, at some geometric or some such rate. Being able to push more advanced nodes that don't have the best yields and not have it be an epic fail allows for ongoing innovation & risk acceptance.

There's the modularity dividends. You can also tune appropriately: just as AMD keeps re-using the IOD across generations, Intel can innovate one piece at a time. This again is extremely liberating from a development perspective, to not have to get everything totally right, to be able to suffer faults, but not in the wafer, but at the design level, where maybe ok the new GPU isn't going to ship in 6 months after all, so we'll keep using the old one, but we can still get the rest of the upgrades out.

There's maybe some power wins. I don't really know how much difference it makes, but Intel just shutting down their CCD and using the on IOD (to use AMD's terms) tiny cores is relishably good. It's easy for me to imagine a big NPU or a big GPU that does likewise. I'm expecting similar from AMD with Medusa Point, their 2027 Big APU (but still sub Medusa Halo, which I cannot frelling wait to see).

I think Intel's been super super smart & has incredible vision about where chipmaking is headed, and has been super ahead of the curve. Alas their P-core has been around in one form or another for a long time & is a bit of a hog, and it's been a disaster for shipping new nodes. But I think they're set up well, and, as frustrating and difficult as it is leaving the convenience of a big chip APU, it feels like that time is here, and Intel's top of class at multi-chip, in a way few others are. We are seeing AMD have to do the same (Medua Point).

Optimal is a suboptimal statement. Only the Sith deal in absolutes, Anakin.